Improvement of Read Performance Using CMOS on Array (COA) in 3D NAND Flash

Abstract

2D NAND flash cells was unable to continue scaling due to several physical limitations including: few electron effects, cell to cell interference and high E-fields under 20 nm design rule. 3D NAND Flash cell was developed to overcome many problems for 2D NAND cell. Also, it has continued to deliver and even accelerate the NAND scaling trends that the data industry demands. This is in part due to its larger gate area and improved electrostatics of the Gate All Around (GAA) architecture using the thin poly silicon channel. It has not only improved the cell characteristics such subthreshold swing and current but also reduced cell interference. As a result, the 3D NAND flash with superior performance has been currently enabled for three and four bit per cell to become mainstream. 3D NAND architectures adapted "poly-Si channels", "word line (WL) replacement for metallization", and "plug etching process". In additionally, to overcome the issue of peripherals taking up too large an area and too high a percentage of the total die size, a few different architectures were proposed. The peripheral circuit (CMOS) can be under array (CUA) and another alternative is to build the peripheral circuits on a different CMOS wafer and then bond the memory wafer with the CMOS wafer using wafer-to wafer micro bonding, termed CMOS bonded array (CBA). Although the two architectures have many advantages for NAND cell, However, still are suffering the degradation of read performance due increased BL RC delay. As NAND stack increases, it should be more challenge due to higher stack. In this paper, the new structure was proposed using NC-vTFT(NAND Cell-vertical TFT) on cell array in vertical NAND (V-NAND) flash memory, for the first time. It will be very promising structure to improve RC delay as NAND cell stack increases.

Received: 10 December 2023 | Revised: 16 April 2024 | Accepted: 10 May 2024

Conflicts of Interest

The authors declare that they have no conflicts of interest to this work.

Data Availability Statement

Data available on request from the corresponding author upon reasonable request.